1. Field of the Invention
The present invention relates to electronic circuits and in particular to electronic circuits in which a central processing unit (CPU) and at least a peripheral unit are used, as is, for example, the case in cryptography controllers.
2. Description of Prior Art
With the increasing use of cashless money transfer, electronic data transmission via public networks and the exchange of credit card numbers via public networks, the demand for cryptography algorithms increases to be able to perform digital signatures, authentifications or encrypting tasks. Well-known cryptography algorithms include asymmetrical encrypting algorithms, such as, for example, the RSA algorithm or processes basing on elliptical curves, or symmetrical encrypting processes, such as, for example, encrypting processes according to the DES or AES standards.
In order to be able to perform the computations specified by the cryptography algorithms with an acceptable speed in everyday life, cryptography controllers specially provided are used. Such cryptography controllers are, for example, used in chip cards, such as, for example, SIM cards or signature cards, for example, for paying by one's mobile phone, for home banking transactions or legally binding electronic signatures. Alternatively, cryptography controllers in computers or servers are used as a safety IC to perform an authentification or to be able to accept encrypting tasks which can, for example, be the safe transmission of credit card numbers, the transmission of emails having confidential contents and the safe cashless money transfer via the Internet.
High demands are made on the cryptography controllers in order for them to satisfy the high demands of users and to be able to establish themselves on the market. In order to be able to guarantee a high algorithmic safety, cryptography controllers must, for example, provide a considerable computing power. The reason for this is that the safety of many cryptographical algorithms, such as, for example, the well-known RSA algorithms, crucially depends on the bit length of the key used, and that consequently the cryptography controllers performing the corresponding cryptography algorithms must be able to cope with numbers of the largest possible length. In the RSA algorithm, for example, key bit lengths of 1,024 bits or sometimes even 2,048 bits have prevailed, present general-purpose processors in comparison operating with 8 bit, 32 bit or 64 bit numbers.
In addition cryptography controllers must comprise a high computing power to be able to perform the computations required for the respective cryptographic algorithm in an appropriate time. Thus it would, for example, be unacceptable for a user to have to wait several minutes for an authentification check or a payment transaction. To achieve high computing powers of this type, well-known cryptography controllers process many computing operations to be performed in parallel to increase the computing speed.
In the usage of cryptography controllers in chip cards, such as, for example, SIM cards or signature cards, an additional problem arises from the fact that they have to be produced cheaply as a mass product. Although they have to process computing-intense algorithms in the shortest time possible, the electronic circuit must not be costly and expensive.
In addition only a restricted amount of energy is available to cryptography controllers so that an additional restriction regarding the circuit effort is thus imposed on the controller design. Terminals for chip cards with contacts, for example, provide a maximum current of 30 mA, wherein in contactless applications and mobile applications, such as, for example, a SIM card in a cell phone, the current may be restricted to less than 10 mA. Consequently the computing speed of the coprocessors is restricted on the one hand by the production cost and on the other hand by the energy available.
A further problem in the design of cryptography controllers arises from the coexistence of many generally conventional cryptography algorithms. In the case of a chip card, for example, that cryptography controller being able to perform the most conventional cryptography algorithms and thus having a broad applicability and a high user-friendliness will establish itself on the market. Such a “multifunctional” cryptography controller, for example, prevents a user from having to carry several chip cards, of which each is provided for a special application or a special cryptography process, respectively. Due to the versatile use, such a multifunctional cryptography controller, however, must be able to perform a variety of computing operations being used by the many cryptographical algorithms, which leads to an increase in complexity or a reduction of the speed of the electronic circuit.
A possible design for a cryptography controller having a high multi-functionality on the one hand and a high processing speed on the other hand consists of an arrangement of a central processing unit and one or several coprocessors operating in parallel, as is, for example, the case in modern personal computers but also in modern graphics cards. An example of a block diagram of such a cryptography controller is shown in FIG. 6. A chip 900 includes a CPU (central processing unit) 910 and several coprocessors 920a and 920b, wherein for reasons of simplification only two coprocessors are shown in FIG. 6. The data connections 930, 940a and 940b of the CPU 910 and of the coprocessors 920a and 920b are connected to one another by a data bus 950. The CPU 910 further includes a data connection 960 being connectable to an external data bus via a connection device 970. In addition the CPU 910 includes a clock connection 980 connected to a clock connection device 1000 via a PLL 990 to receive an external clock signal.
Although the cryptography controller of FIG. 6, by providing several coprocessors 920a and 920b, is suitable for performing various tasks, such as various encrypting algorithms, and for performing computing operations in parallel, one problem of this arrangement is that the entire circuit 900 is clocked by a single external clock signal 1000 and that the PLL 990 consequently is only provided as a clock multiplier for the entire chip 900. IN this circuit it is thus, for example, not possible to clock the CPU 910 and the coprocessors 920a and 920b with different clock frequencies to tune the different computing times required for the tasks to be computed by the coprocessors 920a and 920b to one another by different clock frequencies.
In the design of a chip 900 in CMOS technology, the problem is additionally aggravated by the fact that the power consumption in this case depends on the clock frequency or the switching frequency of the MOSFETs, respectively. If thus some coprocessors are clocked faster than required, more current than necessary will be consumed.
A possible improvement of the cryptography controller design in FIG. 6 is to provide a clock divider for each coprocessor apart from the clock multiplier for the whole chip. A block diagram of such a cryptography controller is shown in FIG. 7, wherein in FIG. 7 equal reference numbers are associated to elements identical to those of FIG. 6. As can be seen, a clock divider 1010a and 1010b is connected between each coprocessor 920a and 920b and the data bus 950, wherein the clock divider is to make it possible that the coprocessors 920a and 920b can be clocked by a certain multiple of the PLL clock. By providing the clock dividers 1010a and 1010b it is thus possible to clock the coprocessors 920a and 920b independent of each other by different multiples of the clock of the CPU 910. In this manner a slowing down of the clock frequency for such coprocessors is enabled, the computation of which either requires less time or the result of which is only required at a later time.
A disadvantage of the circuit 901 of FIG. 7 is that the coprocessors 920a and 920b can only be clocked synchronously by a certain multiple of the clock of the PLL 990. This synchronous clocking with only multiples of the PLL clock on the one hand prevents the necessity of an artificial synchronizing of the coprocessors 920a and 920b but on the other hand also prevents the setting of the clock frequencies of the coprocessor 920a and 920b to clock frequencies not being multiples. In particular it is not possible to clock one or more of the coprocessors 920a and 920b with a clock frequency being faster than the clock frequency of the CPU 910 by another factor than an integer factor, to be, for example, able to perform a very computing-intense modular multiplication faster.